1328 - CS2017 Hardware_Design_exam1

#	Problem	Pass Rate (passed user / total user)
11668	Hardware_Design_exam1_A
11669	Hardware_Design_exam1_B
11670	Hardware_Design_exam1_C
11671	Announcement_exam1

11668 - Hardware_Design_exam1_A

Status | Limits Submit

	Time	Memory

Description

Write a Verilog module, named exam1_A, that models a 1-bit logic unit with and, or, xor and AOI (AND-OR- Invert) functions.

There are three 1-bit inputs a, b, c, one 2-bit input ctr and one 1-bit output d in this logic unit.

You have to copy the sample input and name the file as exam1_A.v.

You may use the provided testbench, which is given in the sample output below ( name it exam1_A_t.v when you hand in) to make sure your design is correct.

You can use either the data flow modeling or behavioral modeling, or any reasonable style.

Do not change the input and output signals.

Note: exam1_B -- https://acm.cs.nthu.edu.tw/problem/11669/

exam1_C -- https://acm.cs.nthu.edu.tw/problem/11670/

Announcement -- https://acm.cs.nthu.edu.tw/problem/11671/

Input

Output

Sample Input Download

// This is exam1_A

module exam1_A(a, b, c, ctr, d);
input a, b, c;
input [1:0] ctr;
output d;
    // add your design here
endmodule

Sample Output Download

// This is testbench for exam1_A

module exam1_A_t;
    reg a, b, c;
    reg [1:0] ctr;
    wire d;
    reg pass;
    
    exam1_A m(.a(a), .b(b), .c(c), .ctr(ctr), .d(d));

    initial begin
        $monitor("%dns a =  %b, b =  %b, c = %b, ctr = %b, d= %b", $time, a, b, c, ctr, d);
        a = 1'b0; b = 1'b0; c = 1'b0; ctr = 2'b00; pass = 1'b1;
        #64 $display("%g Terminating simulation", $time);
        if(pass)
            $display("----------------pass---------------");
        else
            $display("error");

        $finish;
    end
   
    always #2    c = c + 1'b1;
    always #4    b = b + 1'b1;
    always #8    a = a + 1'b1;
    always #16 ctr = ctr + 1'b1;
    
    always @(*) begin
        #1 if(ctr == 2'b00) begin
            if(d != ((a&b)^c)) begin 
                pass = 1'b0;     
                $display("ERROR: d != (a&b)^c");
            end
        end else if(ctr == 2'b01) begin
            if(d !=(a|b|c)) begin 
                pass = 1'b0;     
                $display("ERROR: d != a|b|c ", d, a|b|c);
            end       
        end else if(ctr == 2'b10) begin
            if(d != (a^(b&c))) begin 
                pass = 1'b0;     
                $display("ERROR:d != a^(b&c)");
            end      
        end else begin
            if(d !=( ~((a&b)^c))) begin 
                pass = 1'b0;     
                $display("ERROR:d != ~((a&b)^c)b");
            end       
        end
    end
endmodule

Tags

11669 - Hardware_Design_exam1_B

Status | Limits Submit

	Time	Memory

Description

Implement a 2-digit BCD counter module, exam1_B.

The counter counts up from 00 to 28 repeatedly, the counter would increase by two at the positive edge of every clock cycle. For example, 00 → 02 → 04 → 06 → … → 22 → 24 → 26 → 28 → 00 → 02.

You have to copy the sample input below and name your .v file as exam1_B.v, and you can test your design with the provided testbench in the sample output below.

Please name the .v module and file with exam1_B_t in exam1_B_t.v.

Hint: This design is the same as lab2_2 without the enable signal (which will be much easier)!

Do not change the input and output signals.

Note: exam1_A -- https://acm.cs.nthu.edu.tw/problem/11668/

exam1_C -- https://acm.cs.nthu.edu.tw/problem/11670/

Announcement -- https://acm.cs.nthu.edu.tw/problem/11671/

Input

Output

Sample Input Download

// This is exam1_B.v

module exam1_B (clk, reset, BCD0, BCD1, cout);
input        clk, reset;
output [3:0] BCD0, BCD1;
output       cout;

  always @(posedge clk or posedge reset) begin
     // add your design
  end

endmodule

Sample Output Download

// This is exam1_B_t.v

`timescale 1ns / 1ps

module exam1_B_t;
    reg clk;
    reg reset;
    wire [3:0] BCD0, BCD1;
    wire cout;

    exam1_B test(clk, reset, BCD0, BCD1, cout);

    reg [3:0] preBCD0, preBCD1;
    reg pass;

    initial begin
        $monitor("%5dns : BCD1 : %d, BCD0: %d, cout : %d", $time, BCD1, BCD0, cout);
        clk = 1'b0;
        reset = 1'b0;
        pass = 1;
        #2
        reset = 1'b1;
        #10
        reset = 1'b0;
        #160
        if(pass)
            $display("----------------pass---------------");
        else
            $display("error");

        $finish;
    end
   
    always begin
        #5
        preBCD0 = BCD0;
        preBCD1 = BCD1;
        clk = ~clk;
    end
    
    always @ (posedge clk) begin
        #1
        if(reset == 1) begin
            if(BCD0 != 0 || BCD1 != 0) begin
                printerror(0);
            end
        end
        else begin
            if (preBCD1 == 4'b0010 && preBCD0 == 4'b0110) begin
                if(BCD1 != 4'b0010 || BCD0 != 4'b1000 || cout != 1) begin
                    printerror(1);
                end
            end
            else if (preBCD0 == 4'b1000) begin
                if (preBCD1 <= 4'b0001) begin
                    if (BCD0 != 4'b0000 || BCD1 != (preBCD1 + 4'b0001) || cout != 0) begin
                        printerror(2);
                    end
                end
                else if (preBCD1 == 4'b0010) begin
                    if (BCD0 != 4'b0000 || BCD1 != 4'b0000 || cout != 0) begin
                        printerror(3);
                    end
                end
                else begin
                    printerror(4);
                end
            end
            else begin
                if(BCD0 != (preBCD0 + 4'b0010) || BCD1 != preBCD1 || cout != 0) begin
                    printerror(5);
                end
            end
        end
    end
    
    task printerror;
        input [3:0] error_num;
        begin
            pass=0;
            $display("[NOT_PASS_%1d] : reset : %d, preBCD1 : %d, preBCD0 : %d, BCD1 : %d, BCD0 : %d, cout : %d", error_num, reset, preBCD1, preBCD0, BCD1, BCD0, cout);
        end
    endtask
    
endmodule

Tags

11670 - Hardware_Design_exam1_C

Status | Limits Submit

	Time	Memory

Description

Modify your 2-digit BCD counter to model a 2-digit pingpong counter.

You have to increase/decrease your counter only by pressing the count button.

You must download exam1_C.v and modify it.

Do not change the input and output signals.

Note: exam1_A -- https://acm.cs.nthu.edu.tw/problem/11668/

exam1_B -- https://acm.cs.nthu.edu.tw/problem/11669/

Announcement -- https://acm.cs.nthu.edu.tw/problem/11671/

Input

Output

Sample Input Download

// This is exam1_C.v

`timescale 1ns / 1ps

module LED7SEG(DIGIT, DISPLAY, clk, BCD1, BCD0);
input       clk;
input [3:0] BCD1;
input [3:0] BCD0;
output reg [3:0] DIGIT;
output     [6:0] DISPLAY;

reg [3:0]   value;

    always @ ( posedge clk) begin
        // add your design here
    end

    assign DISPLAY = (value==4'd0) ? 7'b0000001 :
                     (value==4'd1) ? 7'b1001111 :
                     (value==4'd2) ? 7'b0010010 :
                     (value==4'd3) ? 7'b0000110 :
                     (value==4'd4) ? 7'b1001100 :
                     (value==4'd5) ? 7'b0100100 :
                     (value==4'd6) ? 7'b0100000 :
                     (value==4'd7) ? 7'b0001111 :
                     (value==4'd8) ? 7'b0000000 : 
                     (value==4'd9) ? 7'b0000100 :
                                     7'b1111111 ;

endmodule

module clock_divider (clk, clk_div, rst);
    input  clk,rst;
    output clk_div;
    parameter n = 13;
    
    // add your design here

endmodule

module debounce(clk, push_button, button_debounce);
    input  clk, push_button;
    output button_debounce;

    // add your design here

endmodule

module onepulse(clk, button_debounce, one_pulse);
    input  clk, button_debounce;
    output one_pulse;

    // add your design here

endmodule

module exam1_C (DIGIT, DISPLAY, max, min, count, reset, clk);

    input reset;
    input clk;
    input count;
    output [3:0] DIGIT; 
    output [6:0] DISPLAY; 
    output max;
    output min;

// add your design here

endmodule

Sample Output Download

// This is exam1_C.xdc

set_property IOSTANDARD LVCMOS33 [get_ports {DIGIT[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DIGIT[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DIGIT[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DIGIT[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DISPLAY[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DISPLAY[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DISPLAY[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DISPLAY[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DISPLAY[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DISPLAY[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DISPLAY[0]}]
set_property PACKAGE_PIN W4 [get_ports {DIGIT[3]}]
set_property PACKAGE_PIN V4 [get_ports {DIGIT[2]}]
set_property PACKAGE_PIN U4 [get_ports {DIGIT[1]}]
set_property PACKAGE_PIN U2 [get_ports {DIGIT[0]}]
set_property PACKAGE_PIN W7 [get_ports {DISPLAY[6]}]
set_property PACKAGE_PIN W6 [get_ports {DISPLAY[5]}]
set_property PACKAGE_PIN U8 [get_ports {DISPLAY[4]}]
set_property PACKAGE_PIN V8 [get_ports {DISPLAY[3]}]
set_property PACKAGE_PIN U5 [get_ports {DISPLAY[2]}]
set_property PACKAGE_PIN V5 [get_ports {DISPLAY[1]}]
set_property PACKAGE_PIN U7 [get_ports {DISPLAY[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports count]
set_property IOSTANDARD LVCMOS33 [get_ports max]
set_property IOSTANDARD LVCMOS33 [get_ports min]
set_property IOSTANDARD LVCMOS33 [get_ports reset]
set_property PACKAGE_PIN W5 [get_ports clk]
set_property PACKAGE_PIN T18 [get_ports count]
set_property PACKAGE_PIN U18 [get_ports reset]
set_property PACKAGE_PIN U16 [get_ports max]
set_property PACKAGE_PIN E19 [get_ports min]

Tags

11671 - Announcement_exam1

Status | Limits Submit

	Time	Memory

Description

1. You have to make sure that your code follows the requirement or you will get zero score.

2. You have to hand in your code in a ZIP file as exam1_StudentID.zip, including exam1_A.v, exam1_B.v, and the entire folder exam1c (with the whole project, exam1_C.v and BIT file inside), before 2017/11/14 17:30 or you will get zero score.

3. You have to add one comment line in the first line of every Verilog file with the following format :
// StudentID Name

Example:
// 100062000 王小明

4. Hand in your file exam1_StudentID.zip to the address below.

326 教室 -- 192.168.26.66:11404

328 教室（有階梯那間）-- 192.168.28.62:11405

Note: exam1_A -- https://acm.cs.nthu.edu.tw/problem/11668/

exam1_C -- https://acm.cs.nthu.edu.tw/problem/11670/

Announcement -- https://acm.cs.nthu.edu.tw/problem/11671/