Problem 11668

	Time	Memory

Description

Write a Verilog module, named exam1_A, that models a 1-bit logic unit with and, or, xor and AOI (AND-OR- Invert) functions.

There are three 1-bit inputs a, b, c, one 2-bit input ctr and one 1-bit output d in this logic unit.

You have to copy the sample input and name the file as exam1_A.v.

You may use the provided testbench, which is given in the sample output below ( name it exam1_A_t.v when you hand in) to make sure your design is correct.

You can use either the data flow modeling or behavioral modeling, or any reasonable style.

Do not change the input and output signals.

Note: exam1_B -- https://acm.cs.nthu.edu.tw/problem/11669/

exam1_C -- https://acm.cs.nthu.edu.tw/problem/11670/

Announcement -- https://acm.cs.nthu.edu.tw/problem/11671/

Input

Output

Sample Input Download

// This is exam1_A

module exam1_A(a, b, c, ctr, d);
input a, b, c;
input [1:0] ctr;
output d;
    // add your design here
endmodule

Sample Output Download

// This is testbench for exam1_A

module exam1_A_t;
    reg a, b, c;
    reg [1:0] ctr;
    wire d;
    reg pass;
    
    exam1_A m(.a(a), .b(b), .c(c), .ctr(ctr), .d(d));

    initial begin
        $monitor("%dns a =  %b, b =  %b, c = %b, ctr = %b, d= %b", $time, a, b, c, ctr, d);
        a = 1'b0; b = 1'b0; c = 1'b0; ctr = 2'b00; pass = 1'b1;
        #64 $display("%g Terminating simulation", $time);
        if(pass)
            $display("----------------pass---------------");
        else
            $display("error");

        $finish;
    end
   
    always #2    c = c + 1'b1;
    always #4    b = b + 1'b1;
    always #8    a = a + 1'b1;
    always #16 ctr = ctr + 1'b1;
    
    always @(*) begin
        #1 if(ctr == 2'b00) begin
            if(d != ((a&b)^c)) begin 
                pass = 1'b0;     
                $display("ERROR: d != (a&b)^c");
            end
        end else if(ctr == 2'b01) begin
            if(d !=(a|b|c)) begin 
                pass = 1'b0;     
                $display("ERROR: d != a|b|c ", d, a|b|c);
            end       
        end else if(ctr == 2'b10) begin
            if(d != (a^(b&c))) begin 
                pass = 1'b0;     
                $display("ERROR:d != a^(b&c)");
            end      
        end else begin
            if(d !=( ~((a&b)^c))) begin 
                pass = 1'b0;     
                $display("ERROR:d != ~((a&b)^c)b");
            end       
        end
    end
endmodule

11668 - Hardware_Design_exam1_A

Description

Input

Output

Sample Input Download

Sample Output Download

Tags

Discuss

11668 - Hardware_Design_exam1_A

Limits

Description

Input

Output

Sample Input Download

Sample Output Download

Tags

Discuss