Problem 11669

	Time	Memory

Description

Implement a 2-digit BCD counter module, exam1_B.

The counter counts up from 00 to 28 repeatedly, the counter would increase by two at the positive edge of every clock cycle. For example, 00 → 02 → 04 → 06 → … → 22 → 24 → 26 → 28 → 00 → 02.

You have to copy the sample input below and name your .v file as exam1_B.v, and you can test your design with the provided testbench in the sample output below.

Please name the .v module and file with exam1_B_t in exam1_B_t.v.

Hint: This design is the same as lab2_2 without the enable signal (which will be much easier)!

Do not change the input and output signals.

Note: exam1_A -- https://acm.cs.nthu.edu.tw/problem/11668/

exam1_C -- https://acm.cs.nthu.edu.tw/problem/11670/

Announcement -- https://acm.cs.nthu.edu.tw/problem/11671/

Input

Output

Sample Input Download

// This is exam1_B.v

module exam1_B (clk, reset, BCD0, BCD1, cout);
input        clk, reset;
output [3:0] BCD0, BCD1;
output       cout;

  always @(posedge clk or posedge reset) begin
     // add your design
  end

endmodule

Sample Output Download

// This is exam1_B_t.v

`timescale 1ns / 1ps

module exam1_B_t;
    reg clk;
    reg reset;
    wire [3:0] BCD0, BCD1;
    wire cout;

    exam1_B test(clk, reset, BCD0, BCD1, cout);

    reg [3:0] preBCD0, preBCD1;
    reg pass;

    initial begin
        $monitor("%5dns : BCD1 : %d, BCD0: %d, cout : %d", $time, BCD1, BCD0, cout);
        clk = 1'b0;
        reset = 1'b0;
        pass = 1;
        #2
        reset = 1'b1;
        #10
        reset = 1'b0;
        #160
        if(pass)
            $display("----------------pass---------------");
        else
            $display("error");

        $finish;
    end
   
    always begin
        #5
        preBCD0 = BCD0;
        preBCD1 = BCD1;
        clk = ~clk;
    end
    
    always @ (posedge clk) begin
        #1
        if(reset == 1) begin
            if(BCD0 != 0 || BCD1 != 0) begin
                printerror(0);
            end
        end
        else begin
            if (preBCD1 == 4'b0010 && preBCD0 == 4'b0110) begin
                if(BCD1 != 4'b0010 || BCD0 != 4'b1000 || cout != 1) begin
                    printerror(1);
                end
            end
            else if (preBCD0 == 4'b1000) begin
                if (preBCD1 <= 4'b0001) begin
                    if (BCD0 != 4'b0000 || BCD1 != (preBCD1 + 4'b0001) || cout != 0) begin
                        printerror(2);
                    end
                end
                else if (preBCD1 == 4'b0010) begin
                    if (BCD0 != 4'b0000 || BCD1 != 4'b0000 || cout != 0) begin
                        printerror(3);
                    end
                end
                else begin
                    printerror(4);
                end
            end
            else begin
                if(BCD0 != (preBCD0 + 4'b0010) || BCD1 != preBCD1 || cout != 0) begin
                    printerror(5);
                end
            end
        end
    end
    
    task printerror;
        input [3:0] error_num;
        begin
            pass=0;
            $display("[NOT_PASS_%1d] : reset : %d, preBCD1 : %d, preBCD0 : %d, BCD1 : %d, BCD0 : %d, cout : %d", error_num, reset, preBCD1, preBCD0, BCD1, BCD0, cout);
        end
    endtask
    
endmodule

11669 - Hardware_Design_exam1_B

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Output

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11669 - Hardware_Design_exam1_B

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