1. You have to make sure that your code follows the requirement or you will get zero score.
2. You have to hand in your code in a ZIP file as exam1_StudentID.zip, including exam1_A.v, exam1_B.v, and the entire folder exam1c (with the whole project, exam1_C.v and BIT file inside), before 2017/11/14 17:30 or you will get zero score.
3. You have to add one comment line in the first line of every Verilog file with the following format :
// StudentID Name
Example:
// 100062000 王小明
4. Hand in your file exam1_StudentID.zip to the address below.
326 教室 -- 192.168.26.66:11404
328 教室 （有階梯那間）-- 192.168.28.62:11405
Note: exam1_A -- https://acm.cs.nthu.edu.tw/problem/11668/
exam1_C -- https://acm.cs.nthu.edu.tw/problem/11670/
Announcement -- https://acm.cs.nthu.edu.tw/problem/11671/